HDL Compiler

After borrowing the “Dragon Book” from the library, I was interested in trying to write my own compiler. Without ever having looked at VHDL or Verilog, I thought about creating a language to “program” simple digital circuits.

Initially written in C, it is now a Rust application that parses and compiles source code in this hardware description language which I developed myself. It produces files that can be read by my LogicSimulator project, a web-based simulator for digital circuits.

I have written an extensive README containing a lot more details and instructions on how to use the compiler which is available on GitLab together with the source code: gitlab.com/maxkl2/hdl-compiler.

This is how a simple 2-bit counter would be implemented:

sequential block Counter {
    clock rising_edge clk;
    out[2] y;

    y = y + 1#2;
}

block main {
    in clk;
    out[2] y;

    block Counter c;
    c.clk = clk;
    y = c.y;
}

I did not implement any sophisticated graph drawing algorithm, so the circuits are not clearly layed out or aesthetically pleasing. The circuit generated from the code above looks like this:

Example: 16-bit RISC CPU

To ensure the compiler’s correct functionality and to test its limits (especially regarding optimizations) I have written a 16-bit RISC core in this hardware description language: gitlab.com/maxkl2/hdl-cpu. The programs it executes can either be written by hand or created using a simple assembler that I created for this purpose. This assembler, also written in Rust, can be found in the same repository as the core’s HDL code.

This is a part of the circuit as generated by the compiler (yes, it’s ugly):

Here you can see a counter program which also reacts to user input:

The CPU is capable of executing programs with subroutines, stack memory and memory-mapped peripherals. This is an excerpt of the README file, detailing the instruction set of the CPU:

Instruction set

The CPU implements a load/store architecture, inspired by existing RISC architectures such as MIPS and Arm.

There are eight 16-bit registers:

The bits 0-3 of the status register are set by the arithmetic and bitwise instructions as detailed below.

There are currently 22 (out of the possible 32) instructions. Every instruction executes in a single cycle.

The ld and st instructions access the memory, where the “@” sign indicates that a register is interpreted as an absolute address. The letters in the rightmost columns denote the operands as follows:

The jmp/jal instruction can be executed conditionally, with the following possible conditions: